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SM5956A seiko npc corporation ? 6-channel asynchronous sample rate converter overview the SM5956A is a digital audio signal, asynchronous sample rate converter lsi. it reads 6-channel 16/20/24- bit word length input data, and 16/20/24-bit word length output data. it also features a built-in digital deempha- sis ?ter, direct muting and digital audio interface output. features functions l/r 6-channel processing (2-channel stereo, 3-system processing) input sample rate range: 10khz to 200khz output sample rate range: 30khz to 50khz operating sample rate conversion ratio (fso/fsi) *1 0.45 to 4.41 (scksln = l, 512fso operation) 0.225 to 4.41 (scksln = h, 768fso operation) *1 : fsi = input sample rate fso = output sample rate asynchronous input timing and output timing clock inputs system clock input input system clock: 1fsi (lrci) output-system clock: 512fso/768fso (input on sck) deemphasis ?ter function iir ?ter structure 44.1khz, 48khz, 32khz input sample rate fsi compatible direct mute function through mode input data passed directly to the outputs digital audio interface output dia input data undergoes sample rate conver- sion and is output biphase mark encoded output data clocks (lrco, bcko) lrco rate: 1fso bcko rate: 64fso (scksln = l, 512fso operation) 48fso (scksln = h, 768fso operation) slave mode: data is output at a rate dictated by an externally input signal master mode: sample rate is generated internally from the output-system clock, and supplied as an output mcu interface 3-wire serial interface 5v tolerant inputs for direct connection to 5v devices 3.3v single supply package: 48-pin qfp pinout (top view) package dimensions (unit: mm) note. dimensions without tolerance are reference values. ordering information device package SM5956Af 48-pin qfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 vdd lrci bcki dib dic iwl0 iwl1 dia vss imod0 imod1 test4 vdd deemn fs0 fs1 mck mdt mle dmuten throun slaven oediton vss vdd omod1 dito omod0 owl1 owl0 doc dob doa bcko lrco vss vdd test0 test1 test2 test3 sck vss scksln error rstn selfn vss 9 0.4 7 0.1 9 0.4 7 0.1 0.5 0.2 0.125 ? 0.025 + 0.075 1.4 0.1 1.7 max 0.1 0.5 0 ~ 10 0.18 ? 0.05 + 0.09 0.08
SM5956A seiko npc corporation ? features interfaces input data format 2s-complement, msb-?st, l/r alternating serial iis/non-iis formats input word length 16/20/24-bit output data format 2s-complement, msb-?st, l/r alternating serial iis/non-iis format continuous bit clock (64fso/48fso) output word length 16/20/24-bit structure silicon-gate cmos process applications sample rate conversion between digital audio equipment (av ampli?rs, cd-r/rw, md, dvc etc.) sample rate conversion in commercial record- ing/editing equipment converter performance internal data word length: 20 bits deemphasis ?ter characteristics (iir ?ter) gain deviation from ideal ?ter characteristic: 0.03db anti-aliasing lpf characteristics passband ripple: 0.0001db stopband attenuation: > 98db converter noise levels internal calculation noise: ? 96db output round-off noise: 16-bit output mode : ? 98db 20-bit output mode : ? 122db 24-bit output mode : ? 146db format imod1 imod0 iis l l msb-?st left-justi?d l h msb-?st right-justi?d h l msb-?st right-justi?d h h input word length iwl1 iwl0 16 bits l l 20 bits l h 24 bits h l 24 bits h h format omod1 omod0 iis l l msb-?st left-justi?d l h msb-?st right-justi?d h l msb-?st right-justi?d h h output word length owl1 owl0 16 bits l l 20 bits l h 24 bits h l 24 bits h h combined theoretical s/n output word length input word length 16 bits 20 bits 24 bits 16 bits ? 92.3db ? 94.0db ? 94.0db 20 bits ? 94.0db ? 96.0db ? 96.0db 24 bits ? 94.1db ? 96.1db ? 96.2db
SM5956A seiko npc corporation ? block diagram pin description no. name i/o 1 function high low 1 vdd ? vdd supply (3.3v) ?? 2 lrci is sample rate clock input (fsi) ?? 3 bcki is bit clock input (32fsi to 64fsi) ?? 4 dia is data input a ?? 5 dib is data input b ?? 6 dic is data input c ?? 7 iwl0 i input word length select 0 see ?nput interface settings 8 iwl1 i input word length select 1 9 imod0 i input format select 0 10 imod1 i input format select 1 11 test4 id test input test normal 12 vss ? ground (0v) ?? 13 vdd ? vdd supply (3.3v) ?? lrco bcko doa, dob, doc sck lrci bcki scksln input data interface dia, dib, dic conversion rate detector output timing operation imod0 imod1 iwl0 deemn fs0 fs1 output data interface through, mute, and slave mode control dito oediton throun slaven dmuten mck mdt mle digital audio interface iwl1 mcu interface arithmetic operation block deemphasis filter operation interpolation filter operation output operation sequencer block output data operation interpolation operation rstn selfn error omod0 omod1 owl0 owl1
SM5956A seiko npc corporation ? 14 deemn i deemphasis select off on 15 fs0 i deemphasis frequency select 0 see ?ample rate conversion 16 fs1 i deemphasis frequency select 1 17 mck is mcu interface clock input ?? 18 mdt is mcu interface data input ?? 19 mle is mcu interface latch enable input ?? 20 dmuten id direct mute select output mute 21 throun id through-mode select src through 22 slaven id slave-mode select master slave 23 oediton id dit output enable select l output 24 vss ? ground (0v) ?? 25 vdd ? vdd supply (3.3v) ?? 26 dito o digital audio interface output ?? 27 omod1 i output format select 1 see ?utput interface settings 28 omod0 i output format select 0 29 owl1 i output word length select 1 30 owl0 i output word length select 0 31 doc o data output c ?? 32 dob o data output b ?? 33 doa o data output a ?? 34 bcko i/o bit clock input/output (48fso/64fso) ?? 35 lrco i/o sample rate clock input/output (fso) ?? 36 vss ? ground (0v) ?? 37 vdd ? vdd supply (3.3v) ?? 38 test0 id test input test normal 39 test1 id test input test normal 40 test2 id test input test normal 41 test3 id test input test normal 42 sck i output-system clock input (512fso/768fso) ?? 43 vss ? ground (0v) ?? 44 scksln id output-system clock select 768fso 512fso 45 error o input error detector output ?? 46 rstn id reset input ? reset 47 selfn id reset mode select external automatic 48 vss ? ground (0v) ?? 1. i = input, o = output, id = input with pull-down, is = schmitt input, ? = supply no. name i/o 1 function high low
SM5956A seiko npc corporation ? absolute maximum ratings v ss = 0v, vdd pins = v dd note. ratings also apply when power is turned on/off. recommended operating conditions v ss = 0v, vdd pins = v dd parameter symbol rating unit supply voltage v dd ? 0.3 to 4.6 v input voltage v i ? 0.3 to 5.5 v output voltage v o ? 0.3 to v dd + 0.3 v storage temperature t stg ? 55 to 125 c power dissipation p w 700 mw parameter symbol rating unit min typ max supply voltage v dd 3.0 3.3 3.6 v operating temperature t opr ? 40 25 85 c
SM5956A seiko npc corporation ? electrical characteristics dc characteristics v ss = 0v, v dd = 3.0 to 3.6v, ta = ? 40 to 85 c (*a) all outputs no load, system clock frequency f sck = 24.576mhz, input word clock frequency f lrci = 48khz, scksln = l (512fso), supply voltage v dd = 3.3v (*b) all outputs no load, system clock frequency f sck = 36.864mhz, input word clock frequency f lrci = 48khz, scksln = h (768fso), supply voltage v dd = 3.3v note. see ?in classi?ation below for description of pins. pin classi?ation note. the input and input/output pins are all 5v tolerant. the maximum input voltage that can be applied to these pins are 5.5v , if supply voltage is within the recommended operating voltage. if the input voltage is between 5.5v and vdd which is smaller than the recommended operating voltage, the device doesn? breakdown itself, but it maybe generate reverse current from the input pins to the supply voltage (vdd). althoug h input/output pins in input mode can accept 5.5v as the maximum input voltage, the maximum output voltage in output mode is vdd level. it is forbidde n to add more voltage than vdd to output mode bidirectional pins (external pull-up or other means). parameter pin symbol condition rating unit min typ max current consumption vdd i dd (*a) ? 75 90 ma (*b) ? 100 125 input voltage (*1)(*2) (*3)(*5) v ih 2.0 ? 5.5 v v il 0 ? 0.7 v bcko, lrco only 0 ? 0.4 v output voltage (*4)(*5) v oh i oh = ? 2.0ma 2.4 ? v dd v v ol i ol = 2.0ma 0 ? 0.4 v input leakage current (*1)(*2) (*5) i lh v in = v dd ? 1.0 ? 1.0 ? i ll v in = 0v ? 1.0 ? 1.0 ? input current (*3) i ih v in = v dd 12.5 33.0 90.0 ? i il v in = 0v ? 1.0 ? 1.0 ? pull-down resistance (*3) r pd 40 100 240 k ? input load capacity (*1)(*2) (*3)(*5) c ldi ? 10 ? pf symbol type names (*1) inputs sck, imod0, imod1, iwl0, iwl1, deemn, fs0, fs1, omod0, omod1, owl0, owl1 (*2) schmitt inputs lrci, bcki, dia, dib, dic, mck, mdt, mle (*3) pull-down inputs test0, test1, test2, test3, test4, dmuten, throun, slaven, oediton, rstn, selfn, scksln (*4) outputs doa, dob, doc, dito, error (*5) input/outputs bcko, lrco
SM5956A seiko npc corporation ? ac characteristics output-system clock (sck input) reset input (rstn input) note. t cy = output-system clock (sck input) cycle time parameter symbol condition rating unit min typ max clock pulse cycle time t cy scksln = l 39.0 ? 65.1 ns scksln = h 26.0 ? 43.4 high-level clock pulsewidth t cwh scksln = l 15.6 ? 39.1 ns scksln = h 10.4 ? 26.0 low-level clock pulsewidth t cwl scksln = l 15.6 ? 39.1 ns scksln = h 10.4 ? 26.0 clock pulse duty 40 ? 60 % parameter symbol condition rating unit min typ max rstn pulsewidth t rst 4t cy ?? ns t cwh sck t cwl t cy v ih 0.5v dd v il t rst rstn v ih 0.5v dd v il
SM5956A seiko npc corporation ? serial inputs (lrci, bcki, di* inputs) parameter symbol condition rating unit min typ max lrci cycle time t licy 5 ? 100 s bcki pulse cycle time t bicy 78 ? 3125 ns bcki high-level pulsewidth t bicwh 30 ?? ns bcki low-level pulsewidth t bicwl 30 ?? ns di* setup time t dis 30 ?? ns di* hold time t dih 30 ?? ns last bcki rising edge lrci edge t bli 30 ?? ns lrci edge ?st bcki rising edge t lbi 30 ?? ns note. di*: dia, dib, dic pins bcki t bli lrci v ih 0.5v dd v il t lbi v ih 0.5v dd v il di* v ih 0.5v dd v il t dis t dih t bicwh t bicwl t bicy
SM5956A seiko npc corporation ? serial outputs (slaven = l: lrco, bcko inputs, do* outputs) parameter symbol condition rating unit min typ max lrco cycle time t locy 20 ? 33.34 s bcko pulse cycle time t bocy scksln = l 312.5 ? 520.8 ns scksln = h 416.6 ? 694.4 bcko high-level pulsewidth t bocwh scksln = l 93.7 ?? ns scksln = h 125 ?? bcko low-level pulsewidth t bocwl scksln = l 93.7 ?? ns scksln = h 125 ?? last bcko rising edge lrco edge t blo 30 ?? ns lrco edge ?st bcko rising edge t lbo 30 ?? ns do* output delay t dodl c l = 15pf ?? 30 ns note. do*: doa, dob, doc pins bcko t blo lrco v ih 0.5v dd v il t lbo v ih 0.5v dd v il do* v oh 0.5v dd v ol t bocwh t bocwl t bocy t dodl
SM5956A seiko npc corporation ?0 serial outputs (slaven = h: lrco, bcko, do* outputs) note. t cy = output-system clock (sck input) cycle time parameter symbol condition rating unit min typ max lrco cycle time t locy scksln = l ? 512 ? t cy scksln = h ? 768 ? lrco high-level pulsewidth t locwh scksln = l ? 256 ? t cy scksln = h ? 384 ? lrco low-level pulsewidth t locwl scksln = l ? 256 ? t cy scksln = h ? 384 ? bcko pulse cycle time t bocy scksln = l ? 8 ? t cy scksln = h ? 16 ? bcko high-level pulsewidth t bocwh scksln = l ? 4 ? t cy scksln = h ? 8 ? bcko low-level pulsewidth t bocwl scksln = l ? 4 ? t cy scksln = h ? 8 ? bcko output delay t bodl c l = 15pf ?? 30 ns lrco output delay t lodl c l = 15pf ?? 30 ns do* output delay t dodl c l = 15pf ?? 30 ns note. do*: doa, dob, doc pins bcko t bodl lrco v oh 0.5v dd v ol v oh 0.5v dd v ol do* v oh 0.5v dd v ol t bocwh t bocwl t bocy sck v ih 0.5v dd v il t bodl t lodl t dodl
SM5956A seiko npc corporation ?1 mcu interface (mck, mdt, mle inputs) note. t cy = output-system clock (sck input) cycle time parameter symbol condition rating unit min typ max mck cycle time t mcy 60 + 4t cy ?? ns mck high-level pulsewidth t mcwh 30 + 2t cy ?? ns mck low-level pulsewidth t mcwl 30 + 2t cy ?? ns mdt setup time t mds 30 + t cy ?? ns mdt hold time t mdh 30 + t cy ?? ns mle low-level pulsewidth t mlwl 30 + 2t cy ?? ns mle setup time t mls 30 + t cy ?? ns mle hold time t mlh 30 + t cy ?? ns rise time t r ?? 100 ns fall time t f ?? 100 ns mck t mds mdt v ih 0.5v dd v il t mdh v ih 0.5v dd v il mle v ih 0.5v dd v il t mlwl t mcwh t mcwl t mls t mcy t mlh v ih 0.5v dd v il t r 0.8v dd 0.2v dd t f mck mdt mle
SM5956A seiko npc corporation ?2 functional description input interface setting (imod0, imod1, iwl0, iwl1 pins) input data format 2s-complement, msb-?st, l/r alternating serial iis/non-iis format input word length 16/20/24-bit input timing see the timing for each of the input formats in ?ures 1 to 9. output interface settings (omod0, omod1, owl0, owl1, throun, slaven pins) output data format 2s-complement, msb-?st, l/r alternating serial iis/non-iis format continuous bit clock (64fso/48fso) output word length 16/20/24-bit format imod1 imod0 iis l l msb-?st left-justi?d l h msb-?st right-justi?d h l msb-?st right-justi?d h h input word length iwl1 iwl0 16 bits l l 20 bits l h 24 bits h l 24 bits h h format omod1 omod0 iis l l msb-?st left-justi?d l h msb-?st right-justi?d h l msb-?st right-justi?d h h output word length owl1 owl0 16 bits l l 20 bits l h 24 bits h l 24 bits h h
SM5956A seiko npc corporation ?3 output mode select output timing see the timing for each of the output formats in ?ures 10 to 18. in slave mode, note that the lrco and bcko as timing shown in ?ures 10 to 14 must be inputted externally. in through mode, note that the lrci, bcki, di* inputs are passed to the outputs as-is, regardless of the output data format setting, and that dito is a low-level output. note. di*: dia, dib, dic pins do*: doa, dob, doc pins output-system clock (sck, scksln pins) the output-system clock input must have a frequency of either 512fso or 768fso, where fso is the output-sys- tem sampling frequency. in master mode, the lrco and bcko signals are derived from this clock input by frequency division. this clock is also used as the system clock by the internal processing circuits. pins function throun slaven mode description lrco, bcko pin state h h master lrco, bcko are derived by frequency division of the sck input clock. outputs lslave lrco, bcko are supplied externally. when scksln = l, bcko is set to 64fso. when scksln = h, bcko is set to 48fso. inputs l l or h through the lrci, bcki, dia, dib, dic inputs are fed directly to the lrco, bcko, do* outputs. the dito output is low-level. outputs scksln sck input l 512fso (fso = output-system sampling frequency) lrco rate 1fso bcko rate 64fso h 768fso (fso = output-system sampling frequency) lrco rate 1fso bcko rate 48fso
SM5956A seiko npc corporation ?4 system reset (error, rstn pins) under the following conditions, the system must be reset for normal conversion operation. reset occurs using a low-level pulse input on the rstn pin. when power is applied the reset should be released (rstn = l h) after the supply voltage and lrci, bcki, sck (and lrco, bcko in slave mode) clocks have stabilized. when the sck clock is not continuous a reset is required when the sck clock is dynamically switched or is not continuous, such as when switch- ing the sampling frequency or when the clock momentarily stops due to the state of another ic. the reset should be released (rstn = l h) after the sck clock has stabilized. when the lrci, bcki inputs are not continuous (selfn = h) a reset is required when the lrci and bcki clocks are dynamically switched or are not continuous, such as when switching the sampling frequency or when the clock momentarily stops due to the state of another ic. the error pin goes l h to indicate the presence of an input problem, but the lsi continues to operate. the output generated as a result of the non-continuous clocks is not guaranteed, and it is recommended that the outputs be muted externally using dmuten or other means. the reset should be released (rstn = l h) after the lrci and bcki clocks have stabilized. when the lrco, bcko inputs (in slave mode) are not continuous (selfn = h) a reset is required when the lrco and bcko clocks are dynamically switched or are not continuous, such as when switching the sampling frequency or when the clock momentarily stops due to the state of another ic. the error pin goes l h to indicate the presence of a slave input problem, but the lsi continues to operate. the output generated as a result of the non-continuous clocks is not guaranteed, and it is recom- mended that the outputs be muted externally using dmuten or other means. the reset should be released (rstn = l h) after the lrco and bcko clocks have stabilized. a reset is required, in such cases where the error is generated, when the input/output sample rate conversion ratio is set to an incorrect value based on the non-continuous clock, resulting in incorrect output data. output state during the reset interval the doa, dob, doc, and dito are tied low (see ?irect mute?for operation after reset is released). in master mode, the lrco and bcko pins are also tied low. the required time to detect error the error detection block counts input-clock and output-clock for a given times (slaven = l). error pin changes high-level when the observed counts does not agree with the expected counts. therefore it needs some time for error to re?ct a condition of the clock (see table below). in the case of selfn = l, the same time is required to change h l. output frequency [khz] the error by lrci, bcki stopping the error by lrco, bcko stopping min [ms] max [ms] min [ s] max [ s] 32 6.0 8.0 93.8 125.0 44.1 4.3 5.8 68.0 90.7 48 4.0 5.3 62.5 83.3
SM5956A seiko npc corporation ?5 reset mode (selfn pin) the operation after a non-continuous lrci/bcki input clock or lrco/bcko input clock (in slave mode) is detected, as described in ?ystem reset?above, is selected by the selfn pin. direct mute (dmuten pin) direct mute on/off other mute operations direct mute is also applied during reset input cycles. selfn function l automatic self reset when non-continuous input/output clocks are detected. the outputs are directly muted from the time when the non-continuous state is detected until the self reset is released. h the error output goes l h when non-continuous input/output clocks are detected. the output continues as-is during the time an external reset input is applied and released. accordingly, to prevent incorrect output it is recommended that the outputs be directly muted using dmuten or other means. dmuten function l 0 data is output from the next output word. h audio data is output from the next output word. rstn function l 0 data is output from the next output word. h processor data is output after the 8th output word after rstn goes high.
SM5956A seiko npc corporation ?6 mcu interface (mdt, mck, mle pins) the SM5956A has a 3-wire serial mcu interface that is used to set the digital audio interface channel status data. command format the commands from a microcontroller are input using the data input (mdt), bit clock (mck), and load signal (mle) inputs in bit serial format. register table address: 0/h note. each ?g operates using logic-or with its corresponding external input pin of the same name. if only the mcu interface is used for control, all the pins corresponding to the ?gs must be set to their inactive level. when the ?gs are set to their default level, control using external pins is enabled. address: 1/h note. this lsi can accept 4 type category codes shown in the table. write command format bit flag name description default d11 not used set to 0 for normal operation 0 d10 not used set to 0 for normal operation 0 d9 not used set to 0 for normal operation 0 d8 not used set to 0 for normal operation 0 d7 not used set to 0 for normal operation 0 d6 dmuten direct mute ?g 1 d5 throun through mode ?g 1 d4 slaven slave mode ?g 1 d3 oediton dit output enable ?g 1 d2 deemn deemphasis select ?g 1 d1 fs1 deemphasis frequency select ?g 1 0 d0 fs0 deemphasis frequency select ?g 0 0 bit flag name description default d11 cntl0 channel status bit 0 0 d10 cntl1 channel status bit 1 0 d9 cntl2 channel status bit 2. copy ?g 0 d8 cntl3 channel status bit 3. emp ?g 0 d7 catgy0 category code set ?g 0 (catgy1, catgy0) = category (0, 0) = ?00 0000l (cd) (0, 1) = ?00 1100l (dvd) (1, 0) = ?00 0100l (vcd) (1, 1) = ?10 1100l (src) 0 d6 catgy1 category code set ?g 1 0 d5 not used 0 d4 lbit channel status bit 15 0 d3 cfs1 channel status bit 24 0 d2 cfs2 channel status bit 25 0 d1 cp1 channel status bit 28 0 d0 cp2 channel status bit 29 0 a3 a2 a1 a0 d11d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 data 12bit address 4bit mdt mck mle
SM5956A seiko npc corporation ?7 digital audio interface when the oediton pin is low, the digital audio interface output on dito pin is enabled. the input signal on dia is sample rate converted, then a preamble is added and biphase mark encoded to form the output. in through mode, the dito pin is forcibly tied low-level. when the SM5956A is operating in slave mode, the digital interface does not operate whenever the lrco/bcko are not operating as inputs. preamble the preamble is a speci? pattern used for subframe and block synchronization and discrimination. it is assigned to the ?st four time slots (0 to 3) and is represented by 8 consecutive states when biphase mark encoded at the transfer rate. there are 3 preamble patterns. the leading subframe within a block has a b pattern preamble. all other channel 1 subframes have an m pattern preamble, and all channel 2 subframes have a w pattern preamble. note. this lsi starts with a 0, therefore only the preamble for a 0 leading symbol is used. audio sample word and auxiliary data the audio sample word is represented by 20 bits in the digitized audio signal. the auxiliary data has various uses, including ancillary information or audio sample word length extension. the SM5956A audio data, how- ever, is structured in 16-bit words, so bits 4 to 11 are output as 0 data. the audio data is output in bit positions 12 to 27 with the lsb ?st. frame format subframe format preamble channel coding leading symbol: 0 leading symbol: 1 b 11101000 00010111 m 11100010 00011101 w 11100100 00011011 channel 2 m channel 1 w b w m w frame 191 channel 2 channel 1 channel 2 channel 1 frame 1 frame 0 sub frame sub frame start block auxiliary preamble (sync group) audio sample word vucp 03478 2728 31 lsb msb lsb validity flag user data channel status parity bit
SM5956A seiko npc corporation ?8 validity ?g the validity ?g is set to 0 when the audio sample word transferred is valid, and is set to 1 when the data is invalid. the SM5956A sets the validity ?g to 1 when direct mute is turned on. user data the user data are user-de?ed bits originally provided in the standard in response to user requests, but the SM5956A sets all user data bits to 0. channel status the channel status bits can be used to transfer various information, including audio sample word length, pre- emphasis, sampling frequency, time codes, source numbers, and destination codes. the SM5956A sets only 9 bits: cp1, cp2, lbit, cntl0 to 3, cfs1, and cfs2. the 15th bit of the 8th to 15th bit in the category code can be used to set lbit status bit but 8th to 14th bit were determined by the category codes catgy0, 1 (see ?egister table?. all other bits are set to 0. parity bit the parity bit is used to indicate when an odd number of errors occur due to interface problems. the SM5956A sets the parity bit to 1 if the number of 1 bits in the other 27 data bits of the digital audio interface (excluding the preamble) is odd, and sets the parity bit to 0 if the number of 1 bits is even, thereby insuring that the number of 1 bits in the 28-bit data is always even. 01234567891011 0000000000000 12000000000000 24000000000000 36000000000000 ::::::::::::: 1164 000000000000 0123456789101112131415 0 cntl0 cntl1 cntl2 cntl3 0000 0 0 lbit 160000l = 1r = 100 cfs1 cfs2 0 0 cp1 cp2 0 0 320000000000000000 480000000000000000 640000000000000000 800000000000000000 960000000000000000 1120000000000000000 1280000000000000000 1440000000000000000 1600000000000000000 1760000000000000000
SM5956A seiko npc corporation ?9 sample rate conversion the input-to-output sample rate conversion ratio can be arbitrarily set to any value between 0.45 to 4.41 (sck- sln = l, 512fso operation) or 0.225 to 4.41 (scksln = h, 768fso operation). the input-system sample rate (fsi) range is 10khz to 200khz, and the output-system sample rate (fso) range is 30khz to 50khz. however, note that due to system clock frequency limitations, fsi = 44.1khz to fso = 192khz conversion for example is not supported. converter performance internal data word length: 20 bits deemphasis ?ter gain deviation from ideal characteristic: 0.03db anti-aliasing ?ter characteristic: passband ripple 0.0001db stopband attenuation > 98db conversion noise levels internal quantization noise: ? 96db output rounding-off noise: 16-bit output ? 98db 20-bit output ? 122db 24-bit output ? 146db anti-aliasing ?ter characteristics combined output theoretical s/n output word length input word length 16 bits 20 bits 24 bits 16 bits ? 92.3db ? 94.0db ? 94.0db 20 bits ? 94.0db ? 96.0db ? 96.0db 24 bits ? 94.1db ? 96.1db ? 96.2db anti-aliasing ?ter frequency response frequency [ fsi] -120 -100 -80 -60 -40 -20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 attenuation [db]
SM5956A seiko npc corporation ?0 deemphasis (deemn pin) traditional deemphasis ?ters employ an analog circuit construction. this device uses an iir digital ?ter that faithfully reproduces the gain and phase response of analog ?ters. the ?ter coef?ients are selected to match the input sample rate fsi (44.1khz, 48.0khz, 32.0khz), set by the fs0 and fs1 pins. deemphasis on/off deemn = l : deemphasis on deemn = h: deemphasis off deemphasis ?ter coef?ient selection the deemphasis ?ter coef?ients are selected by the fs0 and fs1 pins. deemphasis ?ter characteristics fsi fs0 fs1 44.1khz l l 44.1khz h l 48.0khz l h 32.0khz h h deemphasis ?ter frequency response deemphasis ?ter phase response -12.0 -10.0 -8.0 -6.0 -4.0 -2.0 0.0 10 100 1000 10000 100000 frequency [hz] attenuation [db] 44.1khz 48khz 32khz -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 100000 frequency [hz] phase characteristics [degree] 44.1khz 48khz 32khz
SM5956A seiko npc corporation ?1 group propagation delay t input : serial input data (fsi rate) read end timing (lrci clock rising edge) t output : serial output data (fso rate) output start timing (lrco clock rising edge) cratio : sample rate conversion ratio (fsi/fso) t output ? t input = ((51.791 cratio + 41.557) 36)/fso (at scksln = h, 768fso operation) t output ? t input = ((51.122 cratio + 38.647) 36)/fso (at scksln = l, 512fso operation) response time a certain amount of time is required to calculate the sample rate conversion ratio in the conversion rate detec- tor. assuming as a prerequisite that the SM5956A is supplied with a stable input-system sampling frequency (fsi: input on lrci) and a stable output-system sampling frequency (fso: derived from the sck clock), the time required after system reset to determine the sample rate conversion ratio with 16-bit precision is de?ed as the minimum response time, given by: response time = 28140/fso (638ms at fso = 44.1khz) input frequency fsi [khz] output frequency fso [khz] response time [ms] scksln = l scksln = h 32 44.1 594 285 32 48 557 263 44.1 32 822 406 44.1 48 473 228 48 32 799 403 48 44.1 478 302 32 32 447 395 44.1 44.1 325 287 48 48 298 264 serial data input 1/fsi t input 1/fso serial data output t output t input t output ? t input t output ? t output t input data waveform image
SM5956A seiko npc corporation ?2 timing diagrams input timing (lrci, bcki, dia, dib, dic pins) figure 1. 16-bit msb-?st right-justi?d (imod1 = h, imod0 = h, iwl1 = l, iwl0 = l) bcki = 32fsi to 64fsi figure 2. 20-bit msb-?st right-justi?d (imod1 = h, imod0 = h, iwl0 = l, iwl0 = h) bcki = 40fsi to 64fsi figure 3. 24-bit msb-?st right-justi?d (imod1 = h, imod0 = h, iwl1 = h, iwl0 = h) bcki = 48fsi to 64fsi figure 4. 16-bit msb-?st left-justi?d (imod1 = l, imod0 = h, iwl1 = l, iwl0 = l) bcki = 32fsi to 64fsi figure 5. 20-bit msb-?st left-justi?d (imod1 = l, imod0 = h, iwl1 = l, iwl0 = h) bcki = 40fsi to 64fsi lrci (fsi) bcki (64fsi) dia, dib, dic lch rch 16 15 2 1 16 15 2 1 lrci (fsi) bcki (64fsi) dia, dib, dic 20 19 lch rch 2 1 20 19 2 1 lrci (fsi) bcki (64fsi) dia, dib, dic 24 23 lch rch 24 23 2 1 2 1 lrci (fsi) bcki (64fsi) dia, dib, dic lch rch 16 15 2 1 16 15 2 1 lrci (fsi) bcki (64fsi) dia, dib, dic lch rch 20 19 2 1 20 19 2 1
SM5956A seiko npc corporation ?3 figure 6. 24-bit msb-?st left-justi?d (imod1 = l, imod0 = h, iwl1 = h, iwl0 = h) bcki = 48fsi to 64fsi figure 7. 16-bit iis (imod1 = l, imod0 = l, iwl1 = l, iwl0 = l) bcki = 64fsi only figure 8. 20-bit iis (imod1 = l, imod0 = l, iwl1 = l, iwl0 = h) bcki = 64fsi only figure 9. 24-bit iis (imod1 = l, imod0 = l, iwl1 = h, iwl0 = h) bcki = 64fsi only lrci (fsi) bcki (64fsi) dia, dib, dic lch rch 24 23 2 1 24 23 2 1 lrci (fsi) bcki (64fsi) dia, dib, dic lch rch 16 15 2 1 16 15 2 1 lrci (fsi) bcki (64fsi) dia, dib, dic lch rch 20 19 2 1 20 19 2 1 lrci (fsi) bcki (64fsi) dia, dib, dic lch rch 24 23 2 1 24 23 2 1
SM5956A seiko npc corporation ?4 output timing (lrco, bcko, doa, dob, doc pins) figure 10. 16-bit msb-?st right-justi?d (omod1 = h, omod0 = h, owl1 = l, owl0 = l) bcko = 48fso (scksln = h), 64fso (scksln = l, the above) figure 11. 20-bit msb-?st right-justi?d (omod1 = h, omod0 = h, owl1 = l, owl0 = h) bcko = 48fso (scksln = h), 64fso (scksln = l, the above) figure 12. 24-bit msb-?st right-justi?d (omod1 = h, omod0 = h, owl1 = h, owl0 = h) bcko = 48fso (scksln = h), 64fso (scksln = l, the above) figure 13. 16-bit msb-?st left-justi?d (omod1 = l, omod0 = h, owl1 = l, owl0 = l) bcko = 48fso (scksln = h), 64fso (scksln = l, the above) figure 14. 20-bit msb-?st left-justi?d (omod1 = l, omod0 = h, owl1 = l, owl0 = h) bcko = 48fso (scksln = h), 64fso (scksln = l, the above) lrco (fso) bcko (64fso) doa, dob, doc lch rch 16 15 2 1 16 15 2 1 20 19 lch rch 2 1 20 19 2 1 lrco (fso) bcko (64fso) doa, dob, doc 24 23 lch rch 24 23 2 1 2 1 lrco (fso) bcko (64fso) doa, dob, doc lch rch 16 15 2 1 16 15 2 1 lrco (fso) bcko (64fso) doa, dob, doc lch rch lrco (fso) bcko (64fso) doa, dob, doc 20 19 2 1 20 19 2 1
SM5956A seiko npc corporation ?5 figure 15. 24-bit msb-?st left-justi?d (omod1 = l, omod0 = h, owl1 = h, owl0 = h) bcko = 48fso (scksln = h), 64fso (scksln = l, the above) figure 16. 16-bit iis (omod1 = l, omod0 = l, owl1 = l, owl0 = l) bcko = 48fso (scksln = h), 64fso (scksln = l, the above) figure 17. 20-bit iis (omod1 = l, omod0 = l owl1 = l, owl0 = h) bcko = 48fso (scksln = h), 64fso (scksln = l, the above) figure 18. 24-bit iis (omod1 = l, omod0 = l, owl1 = h, owl0 = h) bcko = 48fso (scksln = h), 64fso (scksln = l, the above) lch rch lrco (fso) bcko (64fso) doa, dob, doc 24 23 2 1 24 23 2 1 lch rch lrco (fso) bcko (64fso) doa, dob, doc 16 15 2 1 16 15 2 1 lch rch lrco (fso) bcko (64fso) doa, dob, doc 20 19 2 1 20 19 2 1 lch rch lrco (fso) bcko (64fso) doa, dob, doc 24 23 2 1 24 23 2 1
SM5956A seiko npc corporation ?6 typical application circuits input interface connection example connection with digital audio interface receiver (dir: cs8414) output interface connection example connection with a most interface transceiver (os8104) deemn lrci bcki dia SM5956Af mcu cc/f0 sel fsync cs12/fck sck sdata m3 m2 m1 m0 dir cs8414 5v iwl0 iwl1 fs0 fs1 cu cbl imod0 imod1 test0 test1 test2 test4 5v test3 5v fsy sck-src fl sr0-d3 most os8104 lrco bcko doa slaven owl0 owl1 SM5956Af 24.576mhz (512fso) sck rmck scksln /rd /wr par cp par src async pad0 pad1 omod0 omod1 throun test0 test1 test2 test4 5v test3
SM5956A seiko npc corporation ?7 nc0412be 2006.04 please pay your attention to the following points at time of using the products shown in this document. the products shown in this document (hereinafter ?roducts? are not intended to be used for the apparatus that exerts harmful in?ence on human lives due to the defects, failure or malfunction of the products. customers are requested to obtain prior written agreeme nt for such use from seiko npc corporation (hereinafter ?pc?. customers shall be solely responsible for, and indemnify and hold npc free and harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. npc reserves the right to change the speci?ations of the products in order to improve the characteristic or reliability thereof. npc makes no claim o r warranty that the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties. therefore, npc shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in t his document. any descriptions including applications, circuits, and the parameters of the products in this document are for reference to use the products, and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further te sting or modi?ation. customers are requested not to export or re-export, directly or indirectly, the products to any country or any ent ity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. customers are req uested appropriately take steps to obtain required permissions or approvals from appropriate government agencies. seiko npc corporation 15-6, nihombashi-kabutocho, chuo-ku, tokyo 103-0026, japan telephone: +81-3-6667-6601 facsimile: +81-3-6667-6611 http://www.npc.co.jp/ email: sales @ npc.co.jp

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